PIPS
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#include <immintrin.h>
Go to the source code of this file.
Macros | |
#define | SIMD_LOAD_V8SF(vec, arr) vec=_mm256_loadu_ps(arr) |
float More... | |
#define | SIMD_LOAD_BROADCAST_V8SF(vec, arr) vec=_mm256_set1_ps(arr) |
#define | SIMD_LOAD_BROADCAST_V4DF(vec, arr) vec=_mm256_set1_pd(arr) |
#define | SIMD_LOADA_V8SF(vec, arr) vec=_mm256_load_ps(arr) |
#define | SIMD_MULPS(vec1, vec2, vec3) vec1=_mm256_mul_ps(vec2,vec3) |
#define | SIMD_DIVPS(vec1, vec2, vec3) vec1=_mm256_div_ps(vec2,vec3) |
#define | SIMD_ADDPS(vec1, vec2, vec3) vec1=_mm256_add_ps(vec2,vec3) |
#define | SIMD_SUBPS(vec1, vec2, vec3) vec1 = _mm256_sub_ps(vec2, vec3) |
#define | SIMD_MULADDPS(vec1, vec2, vec3, vec4) |
#define | SIMD_SHUFFLE_V8SF(dist, src, i0, i1, i2, i3) _mm256_shuffle_pd(src,src,_MM_SHUFFLE(i3,i2,i1,i0)) |
#define | SIMD_SHUFFLE_V4SF(dist, src, i0, i1, i2, i3) _mm256_shuffle_ps(src,src,_MM_SHUFFLE(i3,i2,i1,i0)) |
#define | SIMD_UMINPS(vec1, vec2) |
umin as in unary minus More... | |
#define | SIMD_STORE_V8SF(vec, arr) _mm256_storeu_ps(arr,vec) |
#define | SIMD_STOREA_V8SF(vec, arr) _mm256_store_ps(arr,vec) |
#define | SIMD_STORE_GENERIC_V8SF(vec, v0, v1, v2, v3, v4, v5, v6, v7) |
#define | SIMD_ZERO_V8SF(vec) vec = _mm256_setzero_ps() |
#define | SIMD_LOAD_GENERIC_V8SF(vec, v0, v1, v2, v3, v4, v5, v6, v7) |
#define | SIMD_LOAD_V8SI_TO_V8SF(v, f) |
#define | SIMD_LOAD_V4DF(vec, arr) vec=_mm256_loadu_pd(arr) |
double More... | |
#define | SIMD_MULPD(vec1, vec2, vec3) vec1=_mm256_mul_pd(vec2,vec3) |
#define | SIMD_ADDPD(vec1, vec2, vec3) vec1=_mm256_add_pd(vec2,vec3) |
#define | SIMD_MULADDPD(vec1, vec2, vec3, vec4) |
#define | SIMD_UMINPD(vec1, vec2) |
#define | SIMD_COSPD(vec1, vec2) |
#define | SIMD_SINPD(vec1, vec2) |
#define | SIMD_STORE_V4DF(vec, arr) _mm256_storeu_pd(arr,vec) |
#define | SIMD_STORE_GENERIC_V4DF(vec, v0, v1, v2, v3) |
#define | SIMD_LOAD_GENERIC_V4DF(vec, v0, v1, v2, v3) |
#define | SIMD_STORE_V4DF_TO_V4SF(vec, f) |
conversions More... | |
#define | SIMD_LOAD_V4SF_TO_V4DF(vec, f) |
#define | SIMD_LOADA_V4DI(vec, arr) vec=_mm256_load_si256(arr) |
long long More... | |
#define | SIMD_STOREA_V4DI(vec, arr) vec=_mm256_store_si256(arr) |
#define | SIMD_LOAD_V4DI(vec, arr) vec=_mm256_loadu_si256(arr) |
#define | SIMD_STORE_V4DI(vec, arr) vec=_mm256_storeu_si256(arr) |
#define | SIMD_LOADA_V8SI(vec, arr) vec=_mm256_load_si256(arr) |
int More... | |
#define | SIMD_STOREA_V8SI(vec, arr) vec=_mm256_store_si256(arr) |
#define | SIMD_LOAD_V8SI(vec, arr) vec=_mm256_loadu_si256(arr) |
#define | SIMD_STORE_V8SI(vec, arr) vec=_mm256_storeu_si256(arr) |
#define | SIMD_LOADA_V16HI(vec, arr) vec=_mm256_load_si256(arr) |
short More... | |
#define | SIMD_STOREA_V16HI(vec, arr) vec=_mm256_store_si256(arr) |
#define | SIMD_LOAD_V16HI(vec, arr) vec=_mm256_loadu_si256(arr) |
#define | SIMD_STORE_V16HI(vec, arr) vec=_mm256_storeu_si256(arr) |
#define | SIMD_LOADA_V32QI(vec, arr) vec=_mm256_load_si256(arr) |
char More... | |
#define | SIMD_STOREA_V32QI(vec, arr) vec=_mm256_store_si256(arr) |
#define | SIMD_LOAD_V32QI(vec, arr) vec=_mm256_loadu_si256(arr) |
#define | SIMD_STORE_V32QI(vec, arr) vec=_mm256_storeu_si256(arr) |
Typedefs | |
typedef double a4df[4] | __attribute__((aligned(32))) |
typedef __m256d | v4df |
typedef __m256 | v8sf |
typedef __m128 | v4sf |
typedef __m256i | v4di |
typedef __m256i | v8si |
typedef __m256i | v16hi |
typedef __m256i | v32qi |
#define SIMD_ADDPD | ( | vec1, | |
vec2, | |||
vec3 | |||
) | vec1=_mm256_add_pd(vec2,vec3) |
#define SIMD_ADDPS | ( | vec1, | |
vec2, | |||
vec3 | |||
) | vec1=_mm256_add_ps(vec2,vec3) |
#define SIMD_COSPD | ( | vec1, | |
vec2 | |||
) |
#define SIMD_DIVPS | ( | vec1, | |
vec2, | |||
vec3 | |||
) | vec1=_mm256_div_ps(vec2,vec3) |
#define SIMD_LOAD_BROADCAST_V4DF | ( | vec, | |
arr | |||
) | vec=_mm256_set1_pd(arr) |
#define SIMD_LOAD_BROADCAST_V8SF | ( | vec, | |
arr | |||
) | vec=_mm256_set1_ps(arr) |
#define SIMD_LOAD_GENERIC_V4DF | ( | vec, | |
v0, | |||
v1, | |||
v2, | |||
v3 | |||
) |
#define SIMD_LOAD_GENERIC_V8SF | ( | vec, | |
v0, | |||
v1, | |||
v2, | |||
v3, | |||
v4, | |||
v5, | |||
v6, | |||
v7 | |||
) |
#define SIMD_LOAD_V16HI | ( | vec, | |
arr | |||
) | vec=_mm256_loadu_si256(arr) |
#define SIMD_LOAD_V32QI | ( | vec, | |
arr | |||
) | vec=_mm256_loadu_si256(arr) |
#define SIMD_LOAD_V4DF | ( | vec, | |
arr | |||
) | vec=_mm256_loadu_pd(arr) |
#define SIMD_LOAD_V4DI | ( | vec, | |
arr | |||
) | vec=_mm256_loadu_si256(arr) |
#define SIMD_LOAD_V4SF_TO_V4DF | ( | vec, | |
f | |||
) |
#define SIMD_LOAD_V8SF | ( | vec, | |
arr | |||
) | vec=_mm256_loadu_ps(arr) |
#define SIMD_LOAD_V8SI | ( | vec, | |
arr | |||
) | vec=_mm256_loadu_si256(arr) |
#define SIMD_LOAD_V8SI_TO_V8SF | ( | v, | |
f | |||
) |
#define SIMD_LOADA_V16HI | ( | vec, | |
arr | |||
) | vec=_mm256_load_si256(arr) |
#define SIMD_LOADA_V32QI | ( | vec, | |
arr | |||
) | vec=_mm256_load_si256(arr) |
#define SIMD_LOADA_V4DI | ( | vec, | |
arr | |||
) | vec=_mm256_load_si256(arr) |
#define SIMD_LOADA_V8SI | ( | vec, | |
arr | |||
) | vec=_mm256_load_si256(arr) |
#define SIMD_MULADDPD | ( | vec1, | |
vec2, | |||
vec3, | |||
vec4 | |||
) |
#define SIMD_MULADDPS | ( | vec1, | |
vec2, | |||
vec3, | |||
vec4 | |||
) |
#define SIMD_MULPD | ( | vec1, | |
vec2, | |||
vec3 | |||
) | vec1=_mm256_mul_pd(vec2,vec3) |
#define SIMD_MULPS | ( | vec1, | |
vec2, | |||
vec3 | |||
) | vec1=_mm256_mul_ps(vec2,vec3) |
#define SIMD_SINPD | ( | vec1, | |
vec2 | |||
) |
#define SIMD_STORE_GENERIC_V4DF | ( | vec, | |
v0, | |||
v1, | |||
v2, | |||
v3 | |||
) |
#define SIMD_STORE_GENERIC_V8SF | ( | vec, | |
v0, | |||
v1, | |||
v2, | |||
v3, | |||
v4, | |||
v5, | |||
v6, | |||
v7 | |||
) |
#define SIMD_STORE_V16HI | ( | vec, | |
arr | |||
) | vec=_mm256_storeu_si256(arr) |
#define SIMD_STORE_V32QI | ( | vec, | |
arr | |||
) | vec=_mm256_storeu_si256(arr) |
#define SIMD_STORE_V4DF | ( | vec, | |
arr | |||
) | _mm256_storeu_pd(arr,vec) |
#define SIMD_STORE_V4DF_TO_V4SF | ( | vec, | |
f | |||
) |
#define SIMD_STORE_V4DI | ( | vec, | |
arr | |||
) | vec=_mm256_storeu_si256(arr) |
#define SIMD_STORE_V8SI | ( | vec, | |
arr | |||
) | vec=_mm256_storeu_si256(arr) |
#define SIMD_STOREA_V16HI | ( | vec, | |
arr | |||
) | vec=_mm256_store_si256(arr) |
#define SIMD_STOREA_V32QI | ( | vec, | |
arr | |||
) | vec=_mm256_store_si256(arr) |
#define SIMD_STOREA_V4DI | ( | vec, | |
arr | |||
) | vec=_mm256_store_si256(arr) |
#define SIMD_STOREA_V8SI | ( | vec, | |
arr | |||
) | vec=_mm256_store_si256(arr) |
#define SIMD_SUBPS | ( | vec1, | |
vec2, | |||
vec3 | |||
) | vec1 = _mm256_sub_ps(vec2, vec3) |
#define SIMD_UMINPD | ( | vec1, | |
vec2 | |||
) |
#define SIMD_UMINPS | ( | vec1, | |
vec2 | |||
) |